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mc145200 ? mc145201 motorola 1
include onboard 64/65 prescalers the mc145200 and mc145201 are singlepackage synthesizers with serial interfaces capable of direct usage up to 2.0 ghz. a special architecture makes these plls very easy to program because a byteoriented format is utilized. due to the patented bitgrabber ? registers, no address/steering bits are required for random access of the three registers. thus, tuning can be accomplished via a 3byte serial transfer to the 24bit a register. the interface is both spi and microwire ? compatible. each device features a singleended current source/sink phase detector output and a doubleended phase detector output. both phase detectors have linear transfer functions (no dead zones). the maximum current of the singleended phase detector output is determined by an external resistor tied from the rx pin to ground. this current can be varied via the serial port. the mc145200 features logiclevel converters and highvoltage phase/ frequency detectors; the detector supply may range up to 9.5 v. the mc145201 has lowervoltage phase/frequency detectors optimized for singlesupply systems of 5 v 10%. each part includes a differential rf input which may be operated in a singleended mode. also featured are onboard support of an external crystal and a programmable reference output. the r, a, and n counters are fully programmable. the c register (configuration register) allows the parts to be configured to meet various applications. a patented feature allows the c register to shut off unused outputs, thereby minimizing system noise and interference. in order to have consistent lock times and prevent erroneous data from being loaded into the counters, onboard circuitry synchronizes the update of the a register if the a or n counters are loading. similarly, an update of the r register is synchronized if the r counter is loading. the doublebuffered r register allows new divide ratios to be presented to the three counters (r, a, and n) simultaneously. ? maximum operating frequency: 2000 mhz @ v in = 200 mv pp ? operating supply current: 12 ma nominal ? operating supply voltage range (v dd and v cc pins): 4.5 to 5.5 v ? operating supply voltage range of phase detectors (v pd pin) e mc145200: 8.0 to 9.5 v mc145201: 4.5 to 5.5 v ? current source/sink phase detector output capability: 2 ma maximum ? gain of current source/sink phase/frequency detector controllable via serial port ? operating temperature range: 40 to + 85 c ? r counter division range: (1 and) 5 to 8191 ? dualmodulus capability provides total division up to 262,143 ? highspeed serial interface: 4 mbps ? output a pin, when configured as data out, permits cascading of devices ? two generalpurpose digital outputs e output a: totempole (pushpull) output b: opendrain ? powersaving standby feature with orderly recovery for minimizing lock times, standby current: 30 m a ? evaluation kit available (part numbers mc145200evk and mc145201evk) ? see application note an1253/d for lowpass filter design, and an1277/d for offset reference plls for fine resolution or fast hopping bitgrabber is a trademark of motorola, inc. microwire is a trademark of national semiconductor corp. order this document by mc145200/d semiconductor technical data f in test 2 output b output a clk 12 13 14 15 16 11 10 d in ref in v cc enb 8 7 6 5 4 3 2 1 test 1 rx gnd pd out f v f r ld ref out 9 18 19 20 17 v pd f in v dd pin assignment f suffix sog package case 751j ordering information mc145200f sog package mc145201f sog package MC145200DT tssop mc145201dt tssop dt suffix tssop case 948d 20 1 20 1 ? motorola, inc. 1998 rev 4 1/98 tn98012300
mc145200 ? mc145201 motorola 2 enb ref in d in clk ref out f in f in osc or 4stage divider (configurable) 20 1 18 19 11 10 output a input amp select logic 3 13 24 13stage r counter 64/65 prescaler modulus control logic 12stage n counter 6stage a counter internal control shift register and control logic standby logic por bitgrabber ? a register 24 bits bitgrabber ? c register 8 bits doublebuffered bitgrabber ? r register 16 bits phase/frequency detector b and control phase/frequency detector a and control lock detector and control 6 12 4 2 ld rx pd out f r f v output b (opendrain output) test 2 test 1 9 15 13 4 3 6 8 2 16 supply connections: pin 12 = v cc (v+ to input amp and 64/65 prescaler) pin 5 = v pd (v+ to phase/frequency detectors a and b) pin 14 = v dd (v+ to balance of circuit) pin 7 = gnd (common ground) 17 data out f r f v port block diagram maximum ratings* (voltages referenced to gnd, unless otherwise stated) symbol parameter value unit v cc , v dd dc supply voltage (pins 12 and 14) 0.5 to + 6.0 v v pd dc supply voltage (pin 5) mc145200 mc145201 v dd 0.5 to + 9.5 v dd 0.5 to + 6.0 v v in dc input voltage 0.5 to v dd + 0.5 v v out dc output voltage (except output b, pd out , f r , f v ) 0.5 to v dd + 0.5 v v out dc output voltage (output b, pd out , f r , f v ) 0.5 to v pd + 0.5 v i in , i pd dc input current, per pin (includes v pd ) 10 ma i out dc output current, per pin 20 ma i dd dc supply current, v dd and gnd pins 30 ma p d power dissipation, per package 300 mw t stg storage temperature 65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin descriptions section. this device contains protection circuitry to guard against damage due to high static volt- ages or electric fields. however, precautions must be taken to avoid applications of any volt- age higher than maximum rated voltages to this highimpedance circuit.
mc145200 ? mc145201 motorola 3 electrical characteristics (v dd = v cc = 4.5 to 5.5 v, voltages referenced to gnd, t a = 40 to + 85 c, unless otherwise stated; mc145200: v pd = 8.0 to 9.5 v; mc145201: v pd = 4.5 to 5.5 v with v dd v pd .) symbol parameter test condition guaranteed limit unit v il maximum lowlevel input voltage (d in , clk, enb , ref in ) device in reference mode, dc coupled 0.3 v dd v v ih minimum highlevel input voltage (d in , clk, enb , ref in ) device in reference mode, dc coupled 0.7 v dd v v hys minimum hysteresis voltage (clk, enb ) 300 mv v ol maximum lowlevel output voltage (ref out , output a) i out = 20 m a, device in reference mode 0.1 v v oh minimum highlevel output voltage (ref out , output a) i out = 20 m a, device in reference mode v dd 0.1 v i ol minimum lowlevel output current (ref out , ld, f r , f v ) v out = 0.4 v 0.36 ma i oh minimum highlevel output current (ref out , ld, f r , f v ) v out = v dd 0.4 v for ref out , ld v out = v pd 0.4 v for f r , f v 0.36 ma i ol minimum lowlevel output current (output a, output b) v out = 0.4 v 1.0 ma i oh minimum highlevel output current (output a only) v out = v dd 0.4 v 0.6 ma i in maximum input leakage current (d in , clk, enb , ref in ) v in = v dd or gnd, device in xtal mode 1.0 m a i in maximum input current (ref in ) v in = v dd or gnd, device in reference mode 150 m a i oz maximum output leakage current (pd out ) v out = v pd 0.5 or 0.5 v mc145200 output in highimpedance state mc145201 150 200 na i oz maximum output leakage current (output b) v out = v pd or gnd, output in highimpedance state 10 m a i stby maximum standby supply current (v dd + v pd pins) v in = v dd or gnd; outputs open; device in standby mode, shutdown crystal mode or ref out staticlow reference mode; output b controlling v cc per figure 22 30 m a i pd maximum phase detector quiescent current (v pd pin) bit c6 = high which selects phase detector a, pd out = open, pd out = static low or high, bit c4 = low which is not standby, i rx = 113 m a 600 m a bit c6 = low which selects phase detector b, f r and f v = open, f r and f v = static low or high, bit c4 = low which is not standby 30 i t total operating supply current (v dd + v pd + v cc pins) f in = 2.0 ghz; ref in = 13 mhz @ 1 v pp; output a = inactive and no connect; ref out , f v , f r , pd out , ld = no connect; d in , enb , clk = v dd or gnd, phase detector b enabled (bit c6 = low) * ma * the nominal value = 12 ma. this is not a guaranteed limit.
mc145200 ? mc145201 motorola 4 analog characteristicsecurrent source/sink outputepd out (i out 2 ma, v dd = v cc = 4.5 to 5.5 v, v dd v pd . voltages referenced to gnd) parameter test condition v pd guaranteed limit unit maximum source current variation mc145200: v out = 0.5 v pd 8.0 20 % 9.5 20 mc145201: v out = 0.5 v pd 4.5 20 % 5.5 20 maximum sinkvssource mismatch (note 3) mc145200: v out = 0.5 v pd 8.0 12 % 9.5 12 mc145201: v out = 0.5 v pd 4.5 12 % 5.5 12 output voltage range (note 3) mc145200: i out variation 20% 8.0 0.5 to 7.5 v 9.5 0.5 to 9.0 mc145201: i out variation 20% 4.5 0.5 to 4.0 v 5.5 0.5 to 5.0 notes: 1. percentages calculated using the following formula: (maximum value minimum value) / maximum value. 2. see rx pin description for external resistor values. 3. this parameter is guaranteed for a given temperature within 40 to + 85 c. ac interface characteristics (v dd = 4.5 to 5.5 v, t a = 40 to + 85 c, c l = 50 pf, input t r = t f = 10 ns; mc145200: v pd = 8.0 to 9.5 v; mc145201: v pd = 4.5 to 5.5 v with v dd v pd ) symbol parameter figure no. guaranteed limit unit f clk serial data clock frequency (note: refer to clock t w below) 1 dc to 4.0 mhz t plh , t phl maximum propagation delay, clk to output a (selected as data out) 1, 5 105 ns t plh , t phl maximum propagation delay, enb to output a (selected as port) 2, 5 100 ns t pzl , t plz maximum propagation delay, enb to output b 2, 6 120 ns t tlh , t thl maximum output transition time, output a and output b; t thl only, on output b 1, 5, 6 100 ns c in maximum input capacitance d in , enb , clk, 10 pf timing requirements (v dd = 4.5 to 5.5 v, t a = 40 to + 85 c, input t r = t f = 10 ns unless otherwise indicated) symbol parameter figure no. guaranteed limit unit t su , t h minimum setup and hold times, d in vs clk 3 20 ns t su , t h , t rec minimum setup, hold and recovery times, enb vs clk 4 100 ns t w minimum pulse width, enb 4 * cycles t w minimum pulse width, clk 1 125 ns t r , t f maximum input rise and fall times, clk 1 100 m s * the minimum limit is 3 ref in cycles or 195 f in cycles, whichever is greater.
mc145200 ? mc145201 motorola 5 switching waveforms 10% v dd gnd 1/f clk output a (data out) clk 90% 50% 90% 50% 10% t plh t phl t tlh t thl t w t w t f t r figure 1. enb output a output b 10% v dd gnd 50% 50% t plz t plh t phl 50% t pzl figure 2. d in clk 50% valid 50% t su t h v dd gnd v dd gnd figure 3. clk enb 50% t su t h first clk last clk t rec 50% figure 4. v dd gnd v dd gnd t w t w test point device under test c l * * includes all probe and fixture capacitance. figure 5. test circuit test point device under test c l * * includes all probe and fixture capacitance. figure 6. test circuit + v 7.5 k w
mc145200 ? mc145201 motorola 6 loop specifications (v dd = v cc = 4.5 to 5.5 v unless otherwise indicated, t a = 40 to + 85 c) sbl p t c di i figure guaranteed operating range ui symbol parameter test condition figure no. min max unit v in input voltage range, f in 500 mhz f in 2000 mhz 7 200 1500 mv pp f ref input frequency, ref in mc145200 externally driven in reference mode mc145201 v in 400 mv pp v in 1 v pp v in 400 mv pp v in 1 v pp 8 13 6* 12 4.5* 27 27 27 27 mhz f xtal crystal frequency, crystal mode c1 30 pf, c2 30 pf, includes stray capacitance 9 2 15 mhz f out output frequency, ref out c l = 30 pf 10, 12 dc 10 mhz f operating frequency of the phase detectors dc 2 mhz t w output pulse width, ld, f r , and f v , e mc145200, mc145201 f r in phase with f v , c l = 50 pf, v pd = 5.5 v, v dd = v cc = 5.0 v 11, 12 17 85 ns t tlh , t thl output transition times, ld, f v , and f r e mc145201 c l = 50 pf, v pd = 5.5 v, v dd = v cc = 5.0 v 11, 12 e 65 ns c in input capacitance f in ref in e e tbd 5 pf *if lower frequency is desired, use wave shaping or higher amplitude sinusoidal signal. sine wave generator 1000 pf device under test 1000 pf test point v+ v cc v dd f in f in gnd output a v in 50 w * figure 7. test circuit (f v ) * characteristic impedance sine wave generator 50 w device under test 0.01 m f test point v cc v dd ref in gnd output a v in figure 8. test circuitreference mode (f r ) test point ref out v+ device under test c1 test point v cc v dd output a gnd ref in ref out c2 figure 9. test circuitcrystal mode (f r ) v+ 50% ref out 1/f ref out figure 10. switching waveform
mc145200 ? mc145201 motorola 7 10% 90% output t tlh t thl figure 11. switching waveform 50% t w test point device under test c l * * includes all probe and fixture capacitance. figure 12. test circuit mc145200/mc145201 normalized input impedance at f in e series format (r + jx) (500 mhz to 2 ghz) 3 4 2 1 frequency resistance capacitive capacitance marker (ghz) ( w ) reactance ( w ) (pf) 1 0.5 59.0 240 1.33 2 1 34.7 118 1.35 3 1.5 28.3 68.7 1.54 4 2 37.4 45.7 1.74 f in (pin 11) sog package
mc145200 ? mc145201 motorola 8 pin descriptions digital interface pins d in serial data input (pin 19) the bit stream begins with the most significant bit (msb) and is shifted in on the lowtohigh transition of clk. the bit pattern is 1 byte (8 bits) long to access the c or configuration register, 2 bytes (16 bits) to access the first buffer of the r register, or 3 bytes (24 bits) to access the a register (see table 1). the values in the c, r, and a registers do not change during shifting because the transfer of data to the registers is controlled by enb . caution the value programmed for the ncounter must be greater than or equal to the value of the acounter. the 13 least significant bits (lsbs) of the r register are doublebuffered. as indicated above, data is latched into the first buffer on a 16bit transfer. (the 3 msbs are not double buffered and have an immediate effect after a 16bit trans- fer.) the second buffer of the r register contains the 13 bits for the r counter. this second buffer is loaded with the con- tents of the first buffer when the a register is loaded (a 24bit transfer). this allows presenting new values to the r, a, and n counters simultaneously. if this is not required, then the 16bit transfer may be followed by pulsing enb low with no signal on the clk pin. this is an alternate method of transferring data to the second buffer of the r register (see figure 17). the bit stream needs neither address nor steering bits due to the innovative bitgrabber registers. therefore, all bits in the stream are available to be data for the three registers. random access of any register is provided. that is, the reg- isters may be accessed in any sequence. data is retained in the registers over a supply range of 4.5 to 5.5 v. the formats are shown in figures 15, 16, and 17. d in typically switches near 50% of v dd to maximize noise immunity. this input can be directly interfaced to cmos de- vices with outputs guaranteed to switch near railtorail. when interfacing to nmos or ttl devices, either a level shifter (mc74hc14a, mc14504b) or pullup resistor of 1 k w to 10 k w must be used. parameters to consider when sizing the resistor are worstcase i ol of the driving device, maxi- mum tolerable power consumption, and maximum data rate. table 1. register access (msbs are shifted in first; c0, r0, and a0 are the lsbs) number of clocks accessed register bit nomenclature 8 16 24 other values 32 values > 32 c register r register a register see figure 13 see figures 2225 c7, c6, c5, . . ., c0 r15, r14, r13, . . ., r0 a23, a22, a21, . . ., a0 clk serial data clock input (pin 18) lowtohigh transitions on clk shift bits available at the d in pin, while hightolow transitions shift bits from output a (when configured as data out, see pin 16). the 241/2stage shift register is static, allowing clock rates down to dc in a continuous or intermittent mode. eight clock cycles are required to access the c register. sixteen clock cycles are needed for the first buffer of the r register. twentyfour cycles are used to access the a regis- ter. see table 1 and figures 15, 16, and 17. the number of clocks required for cascaded devices is shown in figures 24 through 26. clk typically switches near 50% of v dd and has a schmitttriggered input buffer. slow clk rise and fall times are allowed. see the last paragraph of d in for more informa- tion. note to guarantee proper operation of the poweron reset (por) circuit, the clk pin must be held at gnd (with enb being a don't care) or enb must be held at the potential of the v+ pin (with clk be- ing a don't care) during powerup. as an alterna- tive, the bit sequence of figure 13 may be used. enb active low enable input (pin 17) this pin is used to activate the serial interface to allow the transfer of data to/from the device. when enb is in an inac- tive high state, shifting is inhibited and the port is held in the initialized state. to transfer data to the device, enb (which must start inactive high) is taken low, a serial transfer is made via d in and clk, and enb is taken back high. the lowtohigh transition on enb transfers data to the c or a registers and first buffer of the r register, depending on the data stream length per table 1. note transitions on enb must not be attempted while clk is high. this puts the device out of synchro- nization with the microcontroller. resynchroniza- tion occurs when enb is high and clk is low. this input is also schmitttriggered and switches near 50% of v dd , thereby minimizing the chance of loading erro- neous data into the registers. see the last paragraph of d in for more information. for por information, see the note for the clk pin . output a configurable digital output (pin 16) output a is selectable as f r , f v , data out, or port. bits a22 and a23 in the a register control the selection; see figure 16. if a23 = a22 = high, output a is configured as f r . this signal is the buffered output of the 13stage r counter. the f r signal appears as normally low and pulses high, and can be used to verify the divide ratio of the r counter. this ratio extends from 5 to 8191 and is determined by the binary value loaded into bits r0 through r12 in the r register. also, direct access to the phase detectors via the ref in pin is allowed by choosing a divide value of 1 (see figure 17). the maximum frequency at which the phase detectors operate is 2 mhz. therefore, the frequency of f r should not exceed 2 mhz.
mc145200 ? mc145201 motorola 9 if a23 = high and a22 = low, output a is configured as f v . this signal is the buffered output of the 12stage n counter. the f v signal appears as normally low and pulses high, and can be used to verify the operation of the prescaler, a counter, and n counter. the divide ratio between the f in in- put and the f v signal is n 64 + a. n is the divide ratio of the n counter and a is the divide ratio of the a counter. these ratios are determined by bits loaded into the a register. see figure 16. the max imum frequency at which the phase detectors operate is 2 mhz. therefore, the frequency of f v should not exceed 2 mhz. if a23 = low and a22 = high, output a is configured as data out. this signal is the serial output of the 241/2stage shift register. the bit stream is shifted out on the hightolow transition of the clk input. upon power up, output a is automatically configured as data out to facilitate cascading devices. if a23 = a22 = low, output a is configured as port. this signal is a generalpurpose digital output which may be used as an mcu port expander. this signal is low when the port bit (c1) of the c register is low, and high when the port bit is high. output b opendrain digital output (pin 15) this signal is a generalpurpose digital output which may be used as an mcu port expander. this signal is low when the out b bit (c0) of the c register is low. when the out b bit is high, output b assumes the highimpedance state. output b may be pulled up through an external resistor or active circuitry to any voltage less than or equal to the poten- tial of the v pd pin. note : the maximum voltage allowed on the v pd pin is 9.5 v for the mc145200 and 5.5 v for the mc145201. upon powerup, poweron reset circuitry forces out- put b to a low level. reference pins ref in and ref out reference input and reference output (pins 20 and 1) configurable pins for a crystal or an external reference. this pair of pins can be configured in one of two modes: the crystal mode or the reference mode. bits r13, r14, and r15 in the r register control the modes as shown in figure 17. in crystal mode, these pins form a reference oscillator when connected to terminals of an external parallelreso- nant crystal. frequencysetting capacitors of appropriate values as recommended by the crystal supplier are con- nected from each of the two pins to ground (up to a maximum of 30 pf each, including stray capacitance). an external re- sistor of 1 m w to 15 m w is connected directly across the pins to ensure linear operation of the amplifier. the device is de- signed to operate with crystals up to 15 mhz; the required connections are shown in figure 8. to turn on the oscillator, bits r15, r14, and r13 must have an octal value of one (001 in binary, respectively). this is the activecrystal mode shown in figure 17. in this mode, the crystal oscillator runs and the r counter divides the crystal frequency, unless the part is in standby. if the part is placed in standby via the c register, the oscillator runs, but the r counter is stopped. however, if bits r15 to r13 have a value of 0, the oscillator is stopped, which saves additional power. this is the shut down crystal mode (shown in figure 17) and can be engaged whether in standby or not. in the reference mode, ref in (pin 20) accepts a signal up to 27 mhz from an external reference oscillator, such as a tcxo. a signal swinging from at least the v il to v ih levels listed in the electrical characteristics table may be directly coupled to the pin. if the signal is less than this level, ac cou- pling must be used as shown in figure 8. due to an on board resistor which is engaged in the reference modes, an external biasing resistor tied between ref in and ref out is not required. with the reference mode, the ref out pin is configured as the output of a divider. as an example, if bits r15, r14, and r13 have an octal value of seven, the frequency at ref out is the ref in frequency divided by 16. in addition, figure 17 shows how to obtain ratios of eight, four, and two. a ratio of onetoone can be obtained with an octal value of three. upon power up, a ratio of eight is automatically initialized. the maximum frequency capability of the ref out pin is 10 mhz. therefore, for ref in frequencies above 10 mhz, the onetoone ratio may not be used. likewise, for ref in frequencies above 20 mhz, the ratio must be more than two. if ref out is unused, an octal value of two should be used for r15, r14, and r13 and the ref out pin should be floated. a value of two allows ref in to be functional while disabling ref out , which minimizes dynamic power consumption and electromagnetic interference (emi). loop pins f in and f in frequency inputs (pins 11 and 10) these pins are frequency inputs from the vco. these pins feed the onboard rf amplifier which drives the 64/65 pres- caler. these inputs may be fed differentially. however, they usually are used in a singleended configuration (shown in figure 7). note that f in is driven while f in must be tied to ground via a capacitor. motorola does not recommend driving f in while terminating f in because this configuration is not tested for sensitivity. the sensitivity is dependent on the frequency as shown in the loop specifications table. pd out singleended phase/freq. detector output (pin 6) this is a threestate currentsource/sink output for use as a loop error signal when combined with an external lowpass filter. the phase/frequency detector is characterized by a lin- ear transfer function (no dead zone). the operation of the phase/ frequency detector is described below and is shown in figure 18. pol bit (c7) in the c register = low (see figure 15) frequency of f v > f r or phase of f v leading f r : current sinking pulses from a floating state frequency of f v < f r or phase of f v lagging f r : current sourcing pulses from a floating state frequency and phase of f v = f r : essentially a floating state; voltage at pin determined by loop filter pol bit (c7) = high frequency of f v > f r or phase of f v leading f r : current sourcing pulses from a floating state frequency of f v < f r or phase of f v lagging f r : current sinking pulses from a floating state
mc145200 ? mc145201 motorola 10 frequency and phase of f v = f r : essentially a floating state; voltage at pin determined by loop filter this output can be enabled, disabled, and inverted via the c register. if desired, pd out can be forced to a floating state by utilization of the disable feature in the c register (bit c6). this is a patented feature. similarly, pd out is forced to the floating state when the device is put into standby (stby bit c4 = high). the pd out circuit is powered by v pd . the phase detector gain is controllable by bits c3, c2, and c1: gain (in amps per radian) = pd out current divided by 2 p . f r and f v (pins 3 and 4) doubleended phase/frequency detector outputs these outputs can be combined externally to generate a loop error signal. through use of a motorola patented tech- nique, the detector's dead zone has been eliminated. there- fore, the phase/frequency detector is characterized by a linear transfer function. the operation of the phase/frequen- cy detector is described below and is shown in figure 18. pol bit (c7) in the c register = low (see figure 15) frequency of f v > f r or phase of f v leading f r : f v = nega- tive pulses, f r = essentially high frequency of f v < f r or phase of f v lagging f r : f v = essen- tially high, f r = negative pulses frequency and phase of f v = f r : f v and f r remain essen- tially high, except for a small minimum time period when both pulse low in phase pol bit (c7) = high frequency of f v > f r or phase of f v leading f r : f r = nega- tive pulses, f v = essentially high frequency of f v < f r or phase of f v lagging f r : f r = essen- tially high, f v = negative pulses frequency and phase of f v = f r : f v and f r remain essen- tially high, except for a small minimum time period when both pulse low in phase these outputs can be enabled, disabled, and inter- changed via c register bits c6 or c4. this is a patented fea- ture. note that when disabled or in standby, f r and f v are forced to their rest condition (high state). the f r and f v output signal swing is approximately from gnd to v pd . ld lock detector output (pin 2) this output is essentially at a high level with narrow low going pulses when the loop is locked (f r and f v of the same phase and frequency). the output pulses low when f v and f r are out of phase or different frequencies. ld is the logical anding of f r and f v (see figure 18). this output can be enabled and disabled via the c register. this is a patented feature. upon power up, onchip initializa- tion circuitry disables ld to a static low logic level to prevent a false alocko signal. if unused, ld should be disabled and left open. the ld output signal swing is approximately from gnd to v dd . rx external resistor (pin 8) a resistor tied between this pin and gnd, in conjunction with bits in the c register, determines the amount of current that the pd out pin sinks and sources. when bits c2 and c3 are both set high, the maximum current is obtained at pd out ; see tables 2 and 3 for other values of current. to achieve a maximum current of 2 ma, the resistor should be about 47 k w when v pd is 9 v or about 18 k w when v pd is 5.0 v. see figure 14 if lower maximum current values are desired. when the f r and f v outputs are used, the rx pin may be floated. test point pins test 1 modulus control signal (pin 9) this pin may be used in conjunction with the test 2 pin for access to the onboard 64/65 prescaler. when test 1 is low, the prescaler divides by 65. when high, the prescaler divides by 64. caution this pin is an unbuffered output and must be floated in an actual application. this pin must be attached to an isolated pad with no trace. test 2 prescaler output (pin 13) this pin may be used to access to the onboard 64/65 prescaler output. caution this pin is an unbuffered output and must be floated in an actual application. this pin must be attached to an isolated pad with no trace. power supply pins v dd positive power supply (pin 14) this pin supplies power to the main cmos digital portion of the device. the voltage range is + 4.5 to + 5.5 v with re- spect to the gnd pin. for optimum performance, v dd should be bypassed to gnd using a lowinductance capacitor mounted very close to these pins. lead lengths on the capacitor should be minimized. v cc positive power supply (pin 12) this pin supplies power to the rf amp and 64/65 pre- scaler. the voltage range is + 4.5 to + 5.5 v with respect to the gnd pin. in the standby mode, the v cc pin still draws a few milliamps from the power supply. this current drain can be eliminated with the use of transistor q1 as shown in figure 22. for optimum performance, v cc should be bypassed to gnd using a lowinductance capacitor mounted very close to these pins. lead lengths on the capacitor should be minimized.
mc145200 ? mc145201 motorola 11 v pd positive power supply (pin 5) this pin supplies power to both phase/frequency detectors a and b. the voltage applied on this pin must be no less than the potential applied to the v dd pin. the maximum voltage can be + 9.5 v with respect to the gnd pin for the mc145200 and + 5.5 v for the mc145201. for optimum performance, v pd should be bypassed to gnd using a lowinductance capacitor mounted very close to these pins. lead lengths on the capacitor should be minimized. gnd ground (pin 7) common ground. 100 ns minimum 12 4 5 31245 31245 3 figure 13. initializing the pll through the serial port note: it may not be convenient to control the enb or clk pins during power up per the pin descriptions. if this is the case, the part may be initialized through the serial port as shown in the figure above. the sequence is similar to accessing the registers except that the clk must remain high at least 100 ns after enb is brought high. note that 3 groups of 5 bits are needed. clk d in enb mc145200 nominal pd out spurious current vs f r frequency (1 v pd out v pd 1v) f r (khz) current (rms na) 10 1.6 20 5.3 50 22 100 95 200 320 mc145201 nominal pd out spurious current vs f r frequency (1 v pd out v pd 1v) f r (khz) current (rms na) 10 3.6 20 4.6 50 17 100 75 200 244 note: for information on spurious current measurement see an1253/d, aan improved pll design method without w n and z o. table 2. pd out current, c1 = low with output a not selected as aporto; also, default mode when output a selected as aporto c3 c2 pd out current 0 0 70% 0 1 80% 1 0 90% 1 1 100% table 3. pd out current, c1 = high with output a not selected as aporto c3 c2 pd out current 0 0 25% 0 1 50% 1 0 75% 1 1 100%
mc145200 ? mc145201 motorola 12 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 i out , source current (ma) w rx, external resistor (k ) v pd = 9.5 v v pd = 8.75 v v pd = 8.0 v pd out current set to 100%; pd out voltage is forced to onehalf of v pd . 0 10 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 i out , source current (ma) pd out current set to 100%; pd out voltage is forced to onehalf of v pd . v pd = 5.5 v v pd = 5.0 v v pd = 4.5 v note: the mc145201 is optimized for rx values in the 18 k w to 40 k w range. for example, to achieve 0.3 ma of output current, it is preferable to use a 30k w resistor for rx and bit settings for 25% (as shown in table 3). w rx, external resistor (k ) nominal mc145200 pd out source current vs rx resistance nominal mc145201 pd out source current vs rx resistance figure 14.
mc145200 ? mc145201 motorola 13 enb clk d in msb lsb c7 c6 c5 c4 c3 c2 c1 c0 1 234 5678 * * at this point, the new byte is transferred to the c register and stored. no other registers are affected. c7 e pol: selects the output polarity of the phase/frequency detectors. when set high, this bit inverts the polarity of pd out and interchanges the f r function with f v as depicted in figure 18. also see the phase detector output pin descriptions for more information. this bit is cleared low at power up. c6 e pda/b: selects which phase/frequency detector is to be used. when set high, enables the output of phase/ frequency detector a (pd out ) and disables phase/frequency detector b by forcing f r and f v to the static high state. when cleared low, phase/frequency detector b is enabled ( f r and f v ) and phase/fre- quency detector a is disabled with pd out forced to the highimpedance state. this bit is cleared low at power up. c5 e lde: enables the lock detector output (ld) when set high. when the bit is cleared low, the ld output is forced to a static low level. this bit is cleared low at power up. c4 e stby: when set high, places the cmos section of device, which is powered by the v dd and v pd pins, in the standby mode for reduced power consumption: pd out is forced to the highimpedance state, f r and f v are forced high, the a, n, and r counters are inhibited from counting, and the rx current is shut off. in standby, the state of ld is determined by bit c5. c5 low forces ld low (no change). c5 high forces ld static high. during standby, data is retained in the a, r, and c registers. the condition of ref/osc circuitry is determined by the control bits in the r register: r13, r14, and r15. however, if ref out = static low is selected, the internal feedback resistor is disconnected and the input is inhibited when in standby; in addition, the ref in input only presents a capacitive load. note: standby does not affect the other modes of the ref/osc circuitry. when c4 is reset low, the part is taken out of standby in 2 steps. first, the ref in (only in one mode) resistor is reconnected, all counters are enabled, and the rx current is enabled. any f r and f v signals are inhibited from toggling the phase/frequency detectors and lock detector. second, when the first f v pulse occurs, the r counter is jam loaded, and the phase/frequency and lock detectors are initial- ized. immediately after the jam load, the a, n, and r counters begin counting down together. at this point, the f r and f v pulses are enabled to the phase and lock detectors. (patented feature.) c3, c2 e i2, i1: controls the pd out source/sink current per tables 2 and 3. with both bits high, the maximum current (as set by rx per figure 14) is available. also, see c1 bit description. c1 e port: when the output a pin is selected as aporto via bits a22 and a23, c1 determines the state of output a. when c1 is set high, output a is forced high; c1 low forces output a low. when output a is not selected as aport,o c1 controls whether the pd out step size is 10% or 25%. (see tables 2 and 3.) when low, steps are 10%. when high, steps are 25%. default is 10% steps when output a is selected as aport.o the port bit is not affected by the standby mode. c0 e out b: determines the state of output b. when c0 is set high, output b is highimpedance; c0 low forces output b low. the out b bit is not affected by the standby mode. this bit is cleared low at power up. figure 15. c register access and format (8 clock cycles are used)
mc145200 ? mc145201 motorola 14 ??? ??? ??? a22 ??? a21 ??? a20 ??? a19 ??? a18 ??? ??? a17 ??? a16 ??? ??? a15 ??? a14 ??? ??? a13 ??? a12 ??? a11 ??? a10 ??? a9 ??? ??? a8 ??? a7 ??? ??? a6 ??? a5 ??? ??? a4 ??? a3 ??? a2 ??? a1 ??? ??? ??? a0 ??? ??? ??? ??? a23 note 3 23456789101112131415161718192021222324 1 1 1 msb lsb 0 0 1 1 0 1 0 1 port d f f v r binary value output a function (note 1) both bits must be high 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 not allowed not allowed not allowed not allowed not allowed n counter = 5 n counter = 6 n counter = 7 . . . f f . . . f f . . . e f n counter = 4094 n counter = 4095 hexadecimal value for n counter 0 0 0 0 3 0 1 2 3 e a counter = 0 a counter = 1 a counter = 2 a counter = 3 a counter = 62 4 1 not allowed hexadecimal value for a counter 3 4 f 0 a counter = 63 not allowed . . . f . . . f not allowed . . . . . . notes: 1. a power-on initialize circuit forces the output a function to default to data out. 2. the values programmed for the n counter must be greater than or equal to the values programmed for the a counter. this results in a total divide value = n x 64 + a. 3. at this point, the three new bytes are transferred to the a register. in addition, the 13 lsbs in the first buffer of the r register are transferred to the r register's second buffer. thus, the r, n, and a counters can be presented new divide ratios at the same time. the first buffer of the r register is not affected. the c register is not affected. enb clk d in figure 16. a register access and format (24 clock cycles are used) out
mc145200 ? mc145201 motorola 15 enb clk d in 12345678 msb lsb r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r11 r12 r13 r14 r15 9 1011 1213 1415 16 0 0 0 0 0 0 0 0 0 f f 0 0 0 0 0 0 0 0 0 f f 0 1 2 3 4 5 6 7 8 e f not allowed r counter = 1 (note 6) not allowed not allowed not allowed r counter = 5 r counter = 6 r counter = 7 r counter = 8 r counter = 8190 r counter = 8191 hexadecimal value 0 0 0 0 0 0 0 0 0 1 1 binary value 0 1 2 3 4 5 6 7 crystal mode, shut down crystal mode, active reference mode, ref in enabled and ref out static low reference mode, ref out = ref in (buffered) reference mode, ref out = ref in /2 reference mode, ref out = ref in /4 reference mode, ref out = ref in /8 (note 3) reference mode, ref out = ref in /16 octal value note 4 note 5 notes: 1. bits r15 through r13 control the configurable aosc or 4stage dividero block (see block diagram). 2. bits r12 through r0 control the a13stage r countero block (see block diagram). 3. a poweron initialize circuit forces a default ref in to ref out ratio of eight. 4. at this point, bits r13, r14, and r15 are stored and sent to the aosc or 4stage dividero block in the block diagram. bits r0 through r12 are loaded into the first buffer in the doublebuffered section of the r register. therefore, the r counter divide ratio is not altered yet and retains the previous ratio loaded. the c and a registers are not affected. 5. at this point, bits r0 through r12 are transferred to the second buffer of the r register. the r counter begins dividing by the new ratio after completing the rest of the present count cycle. clk must be low during the enb pulse, as shown. also, see note 3 of figure 16 for an alternate method of loading the second buffer in the r register. the c and a registers are not affected. the first buffer of the r register is not affected. 6. allows direct access to reference input of phase/frequency detectors. figure 17. r register access and format (16 clock cycles are used)
mc145200 ? mc145201 motorola 16 note: the pd out either sources or sinks current during outoflock conditions. when locked in phase and frequency, the output is high impedance and the voltage at that pin is determined by the lowpass filter capacitor. pd out , f r , and f v are shown with the polarity bit (pol) = low; see figure 14 for pol. f r reference ref in r f v feedback f in (n 64 + a) pd out f r f v ld v h v l sourcing current v h v h v l float v h v l v l v l v h * sinking current v h = high voltage level v l = low voltage level *at this point, when both f r and f v are in phase, the output source and sink circuits are turned on for a short interval. figure 18. phase/frequency detectors and lock detector output waveforms design considerations crystal oscillator considerations the following options may be considered to provide a ref- erence frequency to motorola's cmos frequency synthe- sizers. use of a hybrid crystal oscillator commercially available temperaturecompensated crystal oscillators (tcxos) or crystalcontrolled data clock oscilla- tors provide very stable reference frequencies. an oscillator capable of cmos logic levels at the output may be direct or dc coupled to ref in . if the oscillator does not have cmos logic levels on the outputs, capacitive or ac coupling to ref in may be used (see figure 8). for additional information about tcxos and data clock oscillators, please consult the latest version of the eem elec- tronic engineers master catalog, the gold book, or similar publications. design an offchip reference the user may design an offchip crystal oscillator using discrete transistors or ics specifically developed for crystal oscillator applications, such as the mc12061 mecl device. the reference signal from the mecl device is ac coupled to ref in (see figure 8). for large amplitude signals (standard cmos logic levels), dc coupling may be used. use of the onchip oscillator circuitry the onchip amplifier (a digital inverter) along with an ap- propriate crystal may be used to provide a reference source frequency. a fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in figure 19. the crystal should be specified for a loading capacitance (c l ) which does not exceed approximately 20 pf when used at the highest operating frequency of 15 mhz. assuming r1 = 0 w , the shunt load capacitance (c l ) presented across the crystal can be estimated to be: c l = c in c out c in +c out + c a + c stray + c1 ? c2 c1 + c2 where c in = 5 pf (see figure 20) c out = 6 pf (see figure 20) c a = 1 pf (see figure 20) c1 and c2 = external capacitors (see figure 19) c stray = the total equivalent external circuit stray capacitance appearing across the crystal terminals the oscillator can be atrimmedo onfrequency by making a portion or all of c1 variable. the crystal and associated com- ponents must be located as close as possible to the ref in and ref out pins to minimize distortion, stray capacitance, stray inductance, and startup stabilization time. circuit stray capacitance can also be handled by adding the appropriate stray value to the values for c in and c out . for this approach, the term c stray becomes 0 in the above expression for c l .
mc145200 ? mc145201 motorola 17 power is dissipated in the effective series resistance of the crystal, r e , in figure 21. the maximum drive level specified by the crystal manufacturer represents the maximum stress that the crystal can withstand without damage or excessive shift in operating frequency. r1 in figure 19 limits the drive level. the use of r1 is not necessary in most cases. to verify that the maximum dc supply voltage does not cause the crystal to be overdriven, monitor the output frequency (f r ) at output a as a function of supply voltage. (ref out is not used because loading impacts the oscillator.) the frequency should increase very slightly as the dc supply voltage is increased. an overdriven crystal decreases in fre- quency or becomes unstable with an increase in supply volt- age. the operating supply voltage must be reduced or r1 must be increased in value if the overdriven condition exists. the user should note that the oscillator startup time is pro- portional to the value of r1. through the process of supplying crystals for use with cmos inverters, many crystal manufacturers have devel- oped expertise in cmos oscillator design with crystals. dis- cussions with such manufacturers can prove very helpful (see table 4). recommended reading technical note tn24, statek corp. technical note tn7, statek corp. e. hafner, athe piezoelectric crystal unitdefinitions and method of measuremento, proc. ieee, vol. 57, no. 2, feb. 1969. d. kemper, l. rosine, aquartz crystals for frequency controlo, electrotechnology , june 1969. p. j. ottowitz, aa guide to crystal selectiono, electronic design , may 1966. d. babin, adesigning crystal oscillatorso, machine design , march 7, 1985. d. babin, aguidelines for crystal oscillator designo, machine design , april 25, 1985. r1* c2 c1 frequency synthesizer ref out ref in r f * may be needed in certain cases. see text. figure 19. pierce crystal oscillator circuit figure 20. parasitic capacitances of the amplifier and c stray c in c out c a ref in ref out c stray figure 21. equivalent crystal networks note: values are supplied by crystal manufacturer (parallel resonant crystal). 2 1 2 1 2 1 r s l s c s r e x e c o table 4. partial list of crystal manufacturers motorola e internet address http://motorola.com (search for resonators) united states crystal corp. crystek crystal statek corp. fox electronics note: motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of crystal manufacturers.
mc145200 ? mc145201 motorola 18 f(s) = assuming gain a is very large, then: z(s) = z = w n = phaselocked loop e lowpass filter design (b) a c r 2 c vco (a) f r f v r 1 r 1 r 2 k f k vco nc r 2 sc w n = k f k vco ncr 1 z = w n r 2 c 2 r 2 sc + 1 r 1 sc note: for (b), r 1 is frequently split into two series resistors; each resistor is equal to r 1 divided by 2. a capacitor c c is then placed from the midpoint to ground to further filter the error pulses. the value of c c should be such that the corner frequency of this network does not significantly affect w n . definitions: n = total division ratio in feedback loop k f (phase detector gain) = i pdout /2 p amps per radian for pd out k f (phase detector gain) = v pd /2 p volts per radian for f v and f r k vco (vco transfer function) = 2 pd f vco d v vco for a nominal design starting point, the user might consider a damping factor z 0.7 and a natural loop frequency w n (2 p f r /50) where f r is the frequency at the phase detector input. larger w n values result in faster loop lock times and, for similar sideband filtering, higher f r related vco sidebands. recommended reading: gardner, floyd m., phaselock techniques (second edition). new york, wileyinterscience, 1979. manassewitsch, vadim, frequency synthesizers: theory and design (second edition). new york, wileyinterscience, 1980. blanchard, alain, phaselocked loops: application to coherent receiver design. new york, wileyinterscience, 1976. egan, william f., frequency synthesis by phase lock. new york, wileyinterscience, 1981. rohde, ulrich l., digital pll frequency synthesizers theory and design. englewood cliffs, nj, prenticehall, 1983. berlin, howard m., design of phaselocked loop circuits, with experiments. indianapolis, howard w. sams and co., 1978. kinley, harold, the pll synthesizer cookbook. blue ridge summit, pa, tab books, 1980. seidman, arthur h., integrated circuits applications handbook , chapter 17, pp. 538586. new york, john wiley & sons. fadrhons, jan, adesign and analyze plls on a programmable calculator,o edn . march 5, 1980. an535, phaselocked loop design fundamentals, motorola semiconductor products, inc., 1970. ar254, phaselocked loop design articles, motorola semiconductor products, inc., reprinted with permission from electronic design, 1987. an1253/d, an improved pll design method without w n and z , motorola semiconductor products, inc., 1995. + k vco c n k f 1 + src note: for (a), using k f in amps per radian with the filter's impedance transfer function, z(s), maintains units of volts per radian for the detector/ filter combination. additional sideband filtering can be accomplished by adding a capacitor c across r. the corner w c = 1/rc should be chosen such that w n is not significantly affected. c vco r pd out radians per volt either loop filter (a) or (b) is frequently followed by additional sideband filtering to further attenuate f r related vco sidebands. this addi- tional filtering may be active or passive. = w n rc 2 * the f r and f v outputs are fed to an external combiner/loop filter. the f r and f v outputs swing railtorail. therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter.
mc145200 ? mc145201 motorola 19 threshold detector lowpass filter nc 1000 pf uhf vco integrator mcu optional loop error signals (note 1) +5 v generalpurpose digital output +5 v ref out ref in v cc v dd gnd ld f r f v v pd pd out rx test 1 f in f in test 2 output b output a enb clk d in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 q1 nc + v uhf output buffer note 2 notes: 1. when used, the f r and f v outputs are fed to an external combiner/loop filter. see the phase locked loop e lowpass filter design page for additional information. 2. transistor q1 is required only if the standby feature is needed. q1 permits the bipolar section of the device to be shut down via use of the generalpurpose digital pin, output b. if the standby feature is not needed, tie pin 12 directly to the power supply. 3. for optimum performance, bypass the v cc , v dd , and v pd pins to gnd with lowinductance ca- pacitors. 4. the r counter is programmed for a divide value = ref in /f r . typically, f r is the tuning resolution required for the vco. also, the vco frequency divided by f r = n t = n 64 + a; this determines the values (n, a) that must be programmed into the n and a counters, respectively. figure 22. example application cmos mcu output a (data out) enb clk d in device #1 output a (data out) enb clk d in device #2 optional note: see related figures 24 through 26; these bit streams apply to the mc145190, mc145191, mc145200, and mc145201. figure 23. cascading two devices
mc145200 ? mc145201 motorola 20 1 2 7 8 9 10 15161718 232425 26 31323334 3940 c register bits of device #2 in figure 23 c register bits of device #1 in figure 23 *at this point, the new bytes are transferred to the c registers of both devices and stored. no other registers are affected. x x x c7 c6 c0 x x x x x x c7 c6 c0 ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? * clk enb d in figure 24. accessing the c registers of two cascaded devices 12 8910 15 16 17 23 24 25 31 32 33 39 40 a register bits of device #2 in figure 23 a register bits of device #1 in figure 23 x x a23 a22 a16 a15 a8 a7 a0 a23 a16 ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 46 47 48 55 56 a9 a8 a0 ?? ?? ?? ?? ?? ?? *at this point, the new bytes are transferred to the a registers of both devices and stored. additionally, for both devices, the 13 lsbs in each of the first buffers of the r registers are transferred to the respective r register's second buffer. thus, the r, n, and a counters can be presented new divide ratios at the same time. the first buffer of each r register is not affected. neither c register is affected. * clk enb d in figure 25. accessing the a registers of two cascaded devices
mc145200 ? mc145201 motorola 21 12 8910 15 16 17 23 24 25 31 32 33 r register bits of device #2 in figure 23 r register bits of device #1 in figure 23 x x r15 r14 r8 r7 r0 x x r15 ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 39 40 41 47 48 r8 r7 r0 ?? ?? ?? ?? ?? note 1 note 2 notes applicable to each device: 1. at this point, bits r13, r14, and r15 are stored and sent to the aosc or 4-stage dividero block in the block diagram. bits r0 through r12 are loaded into the first buffer in the double- buffered section of the r register. therefore, the r counter divide ratio is not altered yet and retains the previous ratio loaded. the c and a registers are not affected. 2. at this point, the bits r0 through r12 are transferred to the second buffer of the r register. the r counter begins dividing by the new ratio after completing the rest of the present count cycle. clk must be low during the enb pulse, as shown. also, see note of figure 25 for an alternate method of loading the second buffer in the r register. the c and a registers are not affected. the first buffer of the r register is not affected. clk enb d in figure 26. accessing the r registers of two cascaded devices
mc145200 ? mc145201 motorola 22 package dimensions f suffix sog (small outline gullwing) package case 751j02 0.10 (0.004) seating plane -t- min min max max millimeters inches dim a b c d g j k l m s 0.494 0.201 e 0.014 0.007 0.022 0.002 0 0.291 1.27 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of the d dimension at maximum material condition. 12.55 5.10 e 0.35 0.18 0.55 0.05 0 7.40 12.80 5.40 2.00 0.45 0.23 0.85 0.20 7 8.20 0.504 0.213 0.079 0.018 0.009 0.033 0.008 7 0.323 0.050 bsc -a- -b- 1 10 11 20 g d 20 pl c m s 10 pl l b 0.13 (0.005) m m t 0.13 (0.005) b a m s s k j dt suffix tssop (thin shrunk small outline package) case 948d03 a b l d c g h dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.25 0.002 0.010 f 0.45 0.55 0.018 0.022 g 0.65 bsc 0.026 bsc h 0.275 0.375 0.011 0.015 j 0.09 0.24 0.004 0.009 k 0.16 0.32 0.006 0.013 l 6.30 6.50 0.248 0.256 m 0 10 0 10 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimensions a and b are to be determined at datum plane u. f m k k1 j j1 a a j1 0.09 0.18 0.004 0.007 k1 0.16 0.26 0.006 0.010 0.100 (0.004) section a-a pin 1 identification -t- -u- 0.200 (0.004) m t 20x ref k 20 1 10 11 seating plane
mc145200 ? mc145201 motorola 23 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.: spd, strategic planning office, 141, p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 4321 nishigot anda, shagawaku, tokyo, japan. 0354878488 mfax ? : rmfax0@email.sps.mot.com touchtone 1 6022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 http://sps.motorola.com/mfax/ home page : http://motorola.com/sps/ customer focus center: 18005216274 mc145200/d ?

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